Thursday, 14 Jan @ 9:30 PM
During this webinar, we’ll look at the functions offered in Hart Software Services (HSS) and discuss why it is used in the PolarFire® SoC FPGA design flow. We’ll then configure and build HSS, show you how to program the eNVM with the HSS image and boot the system.
Hugh Breslin is a Design Engineer at Microchip,where he focuseson the test and verification of soft RISC-V® SoCs, along with application development, system development and training for hardened SoC FPGAs and emulation platforms.Healso has a strong focus on software, where he has developed a RISC-V ISA compliance test framework using Microchip’sSoftConsoleIDE and the RISC-V ISA Compliance test suite.
Webinar/Workshop organized by: Microchip
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